A field programmable gate array (FPGA) is a versatile integrated circuit chip, the internal circuitry of which may be configured before packaging by a manufacturer or after packaging by an individual user to realize a user-specific circuit. To configure an FPGA, the user typically configures an on-chip interconnect structure of the FPGA so that selected circuit components in logic modules of the FPGA are electrically connected together in such a way that the resulting circuit is the user-specific circuit desired by the user. In an FPGA employing, for example, amorphous silicon antifuses, selected amorphous silicon antifuses electrically disposed between selected routing conductors in the interconnect structure are "programmed" to connect the selected routing conductors together electrically. Which antifuses are programmed and which antifuses are left unprogrammed determines how the circuit components of the numerous logic modules are interconnected and therefore determines the resulting circuit. FPGAs can employ other types of antifuse structures including, for example, antifuses employing nitrides and oxides. For further details on FPGAs and antifuses, see U.S. Pat. Nos. 5,557,136, 5,544,070, and 5,220,213 all of which are incorporated herein in their entirety.
FIG. 1 (Prior Art) is a simplified illustration of a first logic module 101, an output of which is connected to an input of a second logic module 102 by programmed antifuses 104 and routing conductors 106 of the interconnect structure. Logic module 102 includes a NAND gate 116 shown in detail in FIG. 2 (Prior Art). The seven inputs of NAND gate 116 are labeled 1-7. Transistors 110 and 114 are high voltage protection transistors provided to prevent high voltages present on the interconnect structure during antifuse programming from damaging the logic transistors of the circuit 108 (in this case an inverter) of the logic module output. Protection transistors 110 and 114 are nonconductive during antifuse programming and are conductive during normal circuit operation.
During power up of the FPGA during normal circuit operation (after the FPGA has been programmed and when it is being used by the user), outputs of logic modules which are to supply digital logic HIGHs during the power up period may actually only supply an intermediate voltage. FIG. 3 is a waveform diagram showing the supply voltage V.sub.CC 115 increasing during the power up period. Supply voltage V.sub.CC is supplied to the gate of protection transistor 115 so that protection transistor 115 will be conductive during normal operation so that the output of inverter 108 will be coupled to input 118 of NAND gate 116.
A threshold voltage drop however exists across transistor 114. If inverter 108 outputs a voltage V.sub.CC, node 117 would only be driven to V.sub.CC minus the threshold voltage V.sub.THPT of protection transistor 114 (for example, 1.2 volts) due to this threshold voltage drop were it not for the effect of protection transistor 110. The gate of protection transistor 110 is supplied with a greater charge pump voltage V.sub.CP (for example, 7.8 volts) such that a threshold voltage drop (for example, 1.2 volts) does not occur across transistor 110 during normal circuit operation. Protection transistor 110 therefore conducts the necessary current from the output of inverter 108 to drive input 118 the rest of the way up to V.sub.CC.
Until the voltages V.sub.CC and V.sub.CP reach their appropriate levels (for example, 5.0 volts and 7.8 volts, respectively), however, intermediate voltages are present on those logic module inputs that are to be driven during this power up period with digital logic HIGHs. If, for example, input 7 (see FIG. 2) is at a digital logic LOW and inputs 4-6 are at an intermediate voltage insufficient to turn pmos transistors 214, 218 and 222 completely off, then a current I.sub.CC 225 will flow from supply voltage V.sub.CC, through transistor 228, 214, 218, 222 and 226. Because there are many thousands of these current paths due to the many logic modules in an FPGA, the cumulative total current I.sub.CC may be undesirably large and could be beyond a supply current maximum specified for the device.
FIG. 3 (Prior Art) shows the current spike I.sub.CC that occurs during power up. In the event the FPGA is being powered from a battery, the battery may not be able to supply the large spike of power up current causing the supply voltage V.sub.CC to drop undesirably low during power up.
A method and circuit are desired to prevent such current spikes during power up.